62 WDT_A_hold(WDT_A_BASE);
65 GPIO_setAsPeripheralModuleFunctionOutputPin(
68 GPIO_PRIMARY_MODULE_FUNCTION
72 GPIO_setAsPeripheralModuleFunctionInputPin(
74 GPIO_PIN4 + GPIO_PIN5,
75 GPIO_PRIMARY_MODULE_FUNCTION
84 CS_setDCOFreq(CS_DCORSEL_0, CS_DCOFSEL_3);
86 CS_initClockSignal(CS_ACLK, CS_LFXTCLK_SELECT, CS_CLOCK_DIVIDER_1);
88 CS_initClockSignal(CS_SMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_8);
89 CS_initClockSignal(CS_MCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_8);
91 CS_turnOnLFXT(CS_LFXT_DRIVE_3);
96 RTC_C_holdClock(RTC_C_BASE);
98 RTC_C_enableInterrupt(RTC_C_BASE, RTC_C_PRESCALE_TIMER1_INTERRUPT);
99 RTC_C_definePrescaleEvent(RTC_C_BASE, RTC_C_PRESCALE_1, RTC_C_PSEVENTDIVIDER_128);
101 RTC_C_setCounterValue(RTC_C_BASE, 0);
103 RTC_C_setPrescaleValue(RTC_C_BASE, RTC_C_PRESCALE_0, 0);
105 RTC_C_startClock(RTC_C_BASE);
111 MTIF_setPulseGenPulseGridFreq(MTIF_BASE, MTIF_PULSE_GRID_FREQUENCY_1024HZ);
112 MTIF_clearPulseGenCounter(MTIF_BASE);
113 MTIF_enablePulseGen(MTIF_BASE);
115 MTIF_setPulseGenCountNum(MTIF_BASE, MTIF_KVAL_BIT2);
117 MTIF_clearPulseKCountUpdateRequest(MTIF_BASE);
119 while(MTIF_isPulseKCountUpdated(MTIF_BASE) == MTIF_K_COUNT_IS_NOT_UPDATED);
121 MTIF_enableTestPortOutput(MTIF_BASE);
123 MTIF_enableTestPortTerminalActivationBySWAndHW(MTIF_BASE);
125 MTIF_clearPulseCounter(MTIF_BASE);
126 MTIF_enablePulseCounter(MTIF_BASE);
132 __bis_SR_register(LPM3_bits | GIE);
139 MTIF_setPulseCounterReadRequest(MTIF_BASE);
141 while(MTIF_isPulseCounterReadReady(MTIF_BASE) == MTIF_PULSE_COUNTER_NOT_READY_TO_READ);
145 if(MTIF_getPulseCounterOverflow(MTIF_BASE) == MTIF_PULSE_COUNTER_OVERFLOW)
159 #if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
160 #pragma vector=RTC_C_VECTOR
162 #elif defined(__GNUC__)
163 void __attribute__ ((interrupt(RTC_C_VECTOR)))
RTC_ISR (
void)
165 #error Compiler not supported!
168 switch(__even_in_range(RTCIV, RTCIV__RT1PSIFG))
170 case RTCIV__NONE:
break;
171 case RTCIV__RTCOFIFG:
break;
172 case RTCIV__RTCRDYIFG:
break;
173 case RTCIV__RTCTEVIFG:
176 case RTCIV__RTCAIFG:
break;
177 case RTCIV__RT0PSIFG:
break;
178 case RTCIV__RT1PSIFG:
179 GPIO_toggleOutputOnPin(GPIO_PORT_P1, GPIO_PIN0);
__bic_SR_register_on_exit(LPM3_bits|GIE)
volatile uint32_t pulseCount[10]